This invention relates to microelectronic device structures and, more particularly, to the attachment of a microelectronic chip to a substrate using solder-bump technology.
In one common architecture, a microelectronic chip is fabricated with large numbers of interconnected microelectronic circuits thereon. The microelectronic chip has input and output terminals of the microelectronic circuits on an external surface of the microelectronic chip. A conventional form of the terminals is solder bumps which protrude above the external surface of the microelectronic chip.
A number of the microelectronic chips and other electronic devices may be supported on a substrate. The substrate provides interconnection between the microelectronic chips and also serves as a structural support for the fragile microelectronic chips. The substrate is typically made of a single-layer of ceramic material with electrically conductive traces on its surface, or multiple layers of ceramic with electrically conductive traces on the various levels of the ceramic structure and vertical interconnects between the levels.
The microelectronic chip is attached to the substrate by affixing the solder bumps to the appropriate locations on the conductive traces of the substrate. The affixing is accomplished by fluxing the solder bumps and the traces, contacting the solder bumps to the traces in an oven which heats the solder to a temperature above its melting temperature to cause it to reflow, and then cooling the assembly to below the melting temperature of the solder. The flux is thereafter removed.
The inventor has recognized that the use of the flux may have adverse effects on the microelectronic chip itself. For example, where the microelectronic chip is based on silicon (Si) or gallium arsenide (GaAs) technology, the flux may contaminate the sensitive microcircuits. The flux residue may also result in environmental contamination. The inventor has recognized a need for a joining approach that overcomes these problems that arise from the use of flux-based solder joining of microelectronic chips to substrates. The present invention fulfills this need, and further provides related advantages.
The present invention provides a method for joining microelectronic chips to substrates that avoids the problems associated with conventional solder joining techniques that use a flux. The present approach may be used in a wide variety of applications which accomplish structural and electrical joining of the microelectronic chip to the substrate using a solder-bump or comparable technique. It is applicable to the mass production of microelectronic devices.
In accordance with the invention, a joining method comprises furnishing a microelectronic chip having a chip bonding location thereon, and furnishing a substrate having a substrate bonding location thereon. At least one of the chip bonding location and the substrate bonding location comprises a metallic solder. The chip bonding location is typically a solder bump, and the substrate bonding location is typically an electrically conductive metallic trace. A heating element, preferably a resistance heating element such as a graphite heating element, is furnished. Surface contamination and oxide are removed from the chip bonding location and from the substrate bonding location. Thereafter, the microelectronic chip is joined to the substrate. The step of joining includes positioning the microelectronic chip and the substrate in a facing contact with the chip bonding location and the substrate bonding location in registry in a contact region, and with the heating element disposed adjacent to the chip bonding location and the substrate bonding location to form an assembly. There is no flux present in the assembly in the contact region. The assembly is placed into an oven having a non-oxidizing environment, and the chip bonding location and the substrate bonding location are bonded together. The step of bonding includes the substeps of heating the assembly to a preheating temperature of less than a melting temperature of the solder, and thereafter reflowing the solder by locally heating the contact region to a reflow temperature of greater than the melting temperature of the solder using the heating element. The solder in the contact region is permitted to melt for a reflow period of time above the melting temperature of the solder, and then the contact region is cooled to a temperature below the melting temperature of the solder.
In a preferred application, the removal of surface contamination and oxide is accomplished by plasma cleaning at least one of the chip bonding location and the substrate bonding location, preferably both the chip bonding location and the substrate bonding location. An elapsed transition time between a completion of the step of removing and the commencement of the step of placing is preferably not more than about 30 minutes. The oven desirably has a vacuum, reducing gas, or inert gas environment. The reflow temperature is from about 30xc2x0 C. to about 50xc2x0 C. greater than the melting temperature of the solder, and the reflow period of time is from about 30 to about 100 seconds.
In one particularly preferred combination, the solder material has a composition in weight percent of about 97 percent lead and about 3 percent tin, the reflow temperature is from about 345xc2x0 C. to about 360xc2x0 C., and the reflow time is from about 30 to about 100 seconds.
The present approach does not utilize any flux in the contact region where the chip bonding location and the substrate bonding location meet. The use of the flux is avoided by the cleaning of this area, a transfer to the oven before there is a chance for the metallic surfaces to be re-contaminated or re-oxidized to any substantial degree, and a short reflow time above the melting temperature of the solder. The short reflow time is achieved by preheating the assembly just below the melting temperature of the solder, and then heating it above the melting temperature for a short time using the heating element. Because no flux is used, there is no risk of contamination of the sensitive portions of the microelectronic chip by flux and no need to clean flux from the structure after joining.
Other features and advantages of the present invention will be apparent from the following more detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. The scope of the invention is not, however, limited to this preferred embodiment.